NXP Semiconductors /MIMXRT1021 /SNVS /HPSR

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Interpret as HPSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NOREPORT)HPTA 0 (NOREPORT)PI 0 (LPDIS)LPDIS 0 (BTN)BTN 0 (BI)BI 0 (INIT)SSM_STATE 0 (FAB_CONFIG)SYS_SECURITY_CFG 0 (SYS_SECURE_BOOT)SYS_SECURE_BOOT 0OTPMK_SYNDROME0 (OTPMK_NOT_ZERO)OTPMK_ZERO 0 (ZMK_NOT_ZERO)ZMK_ZERO

PI=NOREPORT, ZMK_ZERO=ZMK_NOT_ZERO, SSM_STATE=INIT, HPTA=NOREPORT, SYS_SECURITY_CFG=FAB_CONFIG, OTPMK_ZERO=OTPMK_NOT_ZERO

Description

SNVS_HP Status Register

Fields

HPTA

HP Time Alarm Indicates that the HP Time Alarm has occurred since this bit was last cleared.

0 (NOREPORT): No time alarm interrupt occurred.

1 (REPORTED): A time alarm interrupt occurred.

PI

Periodic Interrupt Indicates that periodic interrupt has occurred since this bit was last cleared.

0 (NOREPORT): No periodic interrupt occurred.

1 (REPORTED): A periodic interrupt occurred.

LPDIS

Low Power Disable If 1, the low power section has been disabled by means of an input signal to SNVS

BTN

Button Value of the BTN input

BI

Button Interrupt Signal ipi_snvs_btn_int_b was asserted.

SSM_STATE

System Security Monitor State This field contains the encoded state of the SSM’s state machine

0 (INIT): Init

1 (HARD_FAIL): Hard Fail

3 (SOFT_FAIL): Soft Fail

8 (INTERMEDIATE): Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle)

9 (CHECK): Check

11 (NON_SECURE): Non-Secure

13 (TRUSTED): Trusted

15 (SECURE): Secure

SYS_SECURITY_CFG

System Security Configuration This field reflects the three security configuration inputs to SNVS

0 (FAB_CONFIG): Fab Configuration - the default configuration of newly fabricated chips

1 (OPEN_CONFIG): Open Configuration - the configuration after NXP-programmable fuses have been blown

3 (CLOSED_CONFIG): Closed Configuration - the configuration after OEM-programmable fuses have been blown

7 (FIELD_RETURN_CONFIG): Field Return Configuration - the configuration of chips that are returned to NXP for analysis

SYS_SECURE_BOOT

System Secure Boot If SYS_SECURE_BOOT is 1, the chip boots from internal ROM

OTPMK_SYNDROME

One Time Programmable Master Key Syndrome In the case of a single-bit error, the eight lower bits of this value indicate the bit number of error location

OTPMK_ZERO

One Time Programmable Master Key is Equal to Zero

0 (OTPMK_NOT_ZERO): The OTPMK is not zero.

1 (OTPMK_IS_ZERO): The OTPMK is zero.

ZMK_ZERO

Zeroizable Master Key is Equal to Zero

0 (ZMK_NOT_ZERO): The ZMK is not zero.

1 (ZMK_IS_ZERO): The ZMK is zero.

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